Field
Aspects of the present disclosure relate generally to common mode voltage control, and in particular, to a system and method for controlling common mode voltage of an output differential signal of a differential signal processing circuit using a replica circuit and feedback control.
Background
Differential signal processing circuits, such as variable gain amplifiers (VGAs) and continuous time linear equalizers (CTLEs), receive and apply a particular frequency-dependent gain to an input differential signal to generate an output differential signal. The input differential signal is typically received at control terminals (e.g., gates) of input transistors (e.g., field effect transistors (FETs)), and the output differential signal are generated at other terminals (e.g., drains) of the input transistors.
The effective direct current (DC) voltage level of a differential signal is generally referred to as the common mode voltage. The common mode voltage is generally the average voltage between the voltage levels of the positive and negative components of the differential signal. The common mode voltage affects the operating point of the devices to which the differential signal is applied. If the common mode voltage varies, the operating point of the devices varies, which may have undesirable consequences.
In the context of a differential signal processing circuit, the input differential signal applied to the input transistors may have a common mode voltage that varies for a number of reasons. The gain applied to the input differential signal by the differential signal processing circuit results in an output differential signal that has a common mode voltage that varies with the common mode voltage of the input differential signal. In addition, process variation of the differential signal processing circuit itself creates significant common mode voltage variation. As a result, the input transistors are subjected to varying common mode voltage levels, which has the adverse consequence of reducing gain and peaking control for the differential signal processing circuit. Additionally, the varying common mode voltage of the output differential signal may adversely affect the operation of one or more devices downstream of the differential signal processing circuit.